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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ERRIIDR, Implementation Identification Register</h1><p>The ERRIIDR characteristics are:</p><h2>Purpose</h2>
        <p>Defines the implementer of the component.</p>
      <h2>Configuration</h2><p>This register is present only when RAS System Architecture v1p1 is implemented. Otherwise, direct accesses to ERRIIDR are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>ERRIIDR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="12"><a href="#fieldset_0-31_20">ProductID</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">Variant</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">Revision</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">Implementer[10:7]</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">RES0</a></td><td class="lr" colspan="7"><a href="#fieldset_0-6_0">Implementer[6:0]</a></td></tr></tbody></table><h4 id="fieldset_0-31_20">ProductID, bits [31:20]</h4><div class="field">
      <p>Part number, bits [11:0]. The part number is selected by the designer of the component.</p>
    <p>If <a href="ext-errpidr0.html">ERRPIDR0</a> and <a href="ext-errpidr1.html">ERRPIDR1</a> are implemented, <a href="ext-errpidr0.html">ERRPIDR0</a>.PART_0 matches bits [7:0] of ERRIIDR.ProductID and <a href="ext-errpidr1.html">ERRPIDR1</a>.PART_1 matches bits [11:8] of ERRIIDR.ProductID.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-19_16">Variant, bits [19:16]</h4><div class="field"><p>Component major revision.</p>
<p>This field distinguishes product variants or major revisions of the product.</p><p>If <a href="ext-errpidr2.html">ERRPIDR2</a> is implemented, <a href="ext-errpidr2.html">ERRPIDR2</a>.REVISION matches ERRIIDR.Variant.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-15_12">Revision, bits [15:12]</h4><div class="field"><p>Component minor revision.</p>
<p>This field distinguishes minor revisions of the product.</p><p>If <a href="ext-errpidr3.html">ERRPIDR3</a> is implemented, <a href="ext-errpidr3.html">ERRPIDR3</a>.REVAND matches ERRIIDR.Revision.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-11_8">Implementer, bits [11:8, 6:0]</h4><div class="field">
      <p>Contains the JEP106 code of the company that implemented the RAS component. For an Arm implementation, this field has the value <span class="hexnumber">0x43B</span>.</p>
    <p>Bits [11:8] contain the JEP106 continuation code of the implementer, and bits [6:0] contain the JEP106 identity code of the implementer.</p>
<p>If <a href="ext-errpidr4.html">ERRPIDR4</a> is implemented, <a href="ext-errpidr2.html">ERRPIDR2</a> is implemented, and <a href="ext-errpidr1.html">ERRPIDR1</a> is implemented, <a href="ext-errpidr4.html">ERRPIDR4</a>.DES_2 matches bits [11:8] of ERRIIDR.Implementer, <a href="ext-errpidr2.html">ERRPIDR2</a>.DES_1 matches bits [6:4] of ERRIIDR.Implementer, and <a href="ext-errpidr1.html">ERRPIDR1</a>.DES_0 matches bits [3:0] of ERRIIDR.Implementer.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
<p>The Implementer field is split as follows:</p>
<ul>
<li>Implementer[10:7] is ERRIIDR[11:8].
</li><li>Implementer[6:0] is ERRIIDR[6:0].
</li></ul><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-7_7">Bit [7]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h2>Accessing ERRIIDR</h2><h4>ERRIIDR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th></tr><tr><td>RAS</td><td><span class="hexnumber">0xE10</span></td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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